Embodiments of the inventive concept relate generally to positive edge-triggered master-slave flip-flop circuits. More particularly, embodiments of the inventive concept relate to a low-power, small-area, high-speed, positive edge-triggered master-slave flip-flop circuits and devices including the same.
Increased consumer demand for mobile devices such as smart phones and tablet personal computers (PCs) drives ongoing research and development efforts to the design and fabrication of low-power chips. Mobile devices including low-power chips are capable of operating within defined performance parameters over long periods of time by limiting energy consumption (e.g., battery charge). As will be appreciated by those skilled in the art, it is difficult to provide both low power consumption (or extended battery life) and acceptable performance for increasing sophisticated mobile devices.
Many low-power chips include logic circuits configured to process digital signals. Such logic circuits usually include flip-flop circuits and/or latch circuits that are used as data storage elements. That is, flip-flop circuits and latch circuits are able to store, usually in a non-volatile manner, a data state (e.g., a “0” or a “1”) for a particular digital signal. Flip-flop circuits and latch circuits are often functionally configured to form certain types of sequential logic circuits. In general distinction, a latch or latch circuit is a level-sensitive data storage element, while a flip-flop or flip-flop circuit is an edge-sensitive data storage element.
Within a constituent mobile device, the power consumed by flip-flop circuits and latch circuits is an important design consideration. Yet, increasing performance demands placed upon contemporary mobile devices requires faster and faster operating speeds for flip-flop circuits and latch circuits which tends to increase overall power consumption. Thus, continuing efforts are being made to reduce the power consumption of flip-flop circuits and latch circuits while still providing acceptable operating speeds.